I was wondering what system or communication protocol the brain uses to communicate with the battery. I assume it uses the two pins on the connector that aren’t labeled positive and negative but I can’t figure out how it’s working exactly. The point of knowing how it communicates is so I can possibly read the signaling with a different computer and use the information.
They might not have a + and - but they could be color coded. Red wires are +, and Black is -.
On the brain and battery two of the 4 pins are labeled with a plus and minus respectively. My assumption is that those two are used for power. The other two therefore must be the data pins. I just don’t know what protocol the data is transmitted in.
One is a data pin, it’s bi-directional half duplex communication. The other pin is used to wake the battery if it’s sleeping (which happens after a few minutes of being disconnected). The communications protocol is proprietary to VEX.
This makes me curious…
Do you know of the reasons as to why the batteries need to be updated so frequently whenever the V5 brain gets updated?
We haven’t had a battery firmware update for 2 years, 1.0.9 was the last version of vexos with a battery update.
Dedicating two beefy copper wires - one just to wake up the battery and another to transmit small amounts of data seems wasteful.
I was wondering if, during the V5 design phase, some sort of wire reduction was considered to communicate between V5 brain and battery over the same 2 wires that deliver the battery power?
You can easily get chips that implement UART to PLC functionality from multiple manufacturers. For example: SIG100 family, MAX20340EWL, or SN65HVD96 that is a relative of SN65HVD1782, which is used inside V5 brain for every port.
(TI Source: Using SN65HVD96 to Create a Power-Over-Data and Polarity Immunity Solution)
I understand that at a time the cost of extra copper in the cable and the custom cable connectors might have been slightly cheaper than the cost of extra electronic components and extra inductors for filtering… But what was the reasoning anyway?
My guess is the reasoning is exactly that. It’s cheaper and less complex than a DC power/data bus system.
Thank you very much. I would ask for specific info on the protocol but my guess is that’s not information VEX wants to share.